5

I have simple question, why do we use in computers today synchronous memory? Is there some advantage over asynchronous?

quack quixote
  • 42,186
  • 14
  • 105
  • 129
user32569
  • 799
  • 1
  • 12
  • 22

2 Answers2

1

There's a good overview at Ars Technica on RAM.

Chris S
  • 6,084
  • 21
  • 21
  • "async you assert the address you want to read, then wait a fixed amount of time" I don't actually know a lot about this, but that doesn't seem accurate. – Earlz May 04 '10 at 18:50
  • +1 for your link being good. -1 because you don't seem to have read it. It says nothing about fixed times. Infact, async. is suppose to be the exact opposite of fixed, where as sync. is fixed (in clock cycle time) – Earlz May 04 '10 at 18:52
  • Accepted for GREAT link. – user32569 May 07 '10 at 16:35
  • @Earlz You have it the other way around. You don't wait a fixed amount of time in a sync system, you wait some number of clock cycles. That can vary depending on where in the clock cycle you were when you output the information. However, with async, you do wait a fixed amount of time (because there aren't any clock cycles), whatever the access time of the memory is. The difference is precisely that with async you have some fixed amount of time that's the memory's access time whereas with sync, you track clock edges. – David Schwartz Nov 06 '17 at 05:14
  • An excellent guide on RAM that's still very good even now in 2021. The archived links unfortunately don't have any of the original pictures anymore. But I was able to find Part 1 of the guide on Ars Technica's new site (which has pics): https://arstechnica.com/gadgets/2000/07/ram-guide-part1-1/ Unfortunately couldn't find it for Part 2. – Jethro Cao Feb 16 '21 at 07:01
0

As usual, Wikipedia does a better job of explaining than I could, but the important bit seems to be:

SDRAM has a synchronous interface, meaning that it waits for a clock signal before responding to control inputs and is therefore synchronized with the computer's system bus. The clock is used to drive an internal finite state machine that pipelines incoming instructions. This allows the chip to have a more complex pattern of operation than an asynchronous DRAM, which does not have a synchronized interface.

Stephen Jennings
  • 23,171
  • 5
  • 72
  • 107